Optical receivers are illuminated with optical input beams and respond by generating either optical or electrical output signals. These receivers are now being fabricated as the input stages of very large scale integrated (VLSI) circuits on semiconductor chips for use in communications equipment, and thus their performance characteristics must be improved.
A typical prior art optical receiver circuit has a detector stage comprising two photo-diodes connected in series having a first electrical node between them, and an input stage comprising two field-effect transistors (FETs), a load FET and an input FET, connected in series. The gate input of the input FET is connected to the first electrical node. The output of the receiver circuit is taken from a second electrical node located between the FETs. A first optical input beam incident on the first photo-diode causes a first logic level output to be generated, and a complementary optical input beam alternately incident on the second photo-diode causes a second logic level output to be generated.
One problem that arises in VLSI circuit arrays is controlling the allowed voltages and voltage swings that are present at such optical receivers. If these voltages are not controlled, the input light beams must have large optical energies to ensure sufficient voltage swings to switch the input FET to the desired state. One approach for controlling the voltage swing is to use clamping diodes at the detector stage. However, additional clamping diode voltages are then required, which complicates system design since two additional voltage power supplies for each receiver circuit are then typically needed.
Further, the clamping diode voltages must be carefully set relative to the local voltage levels of the circuit. These local voltages may vary from place to place on a semiconductor chip. Therefore, maintaining optimum clamping conditions across an entire chip may be difficult.
Yet further, the input FET threshold must be considered when setting the clamping diode voltages. Since threshold variations may exist across a chip or between chips, and since different chips may require different voltages, system design is further complicated.